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3.3V 1M x 64-Bit EDO-DRAM Module 3.3V 1M x 72-Bit EDO-DRAM Module 168pin unbuffered DIMM Module with serial presence detect
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HYM64V1005GU-50/-60 HYM72V1005GU-50/-60
168 Pin JEDEC Standard, Unbuffered 8 Byte Dual In-Line Memory Module for PC main memory applications 1 bank 1M x 64, 1M x 72 organisation Optimized for byte-write non-parity or ECC applications Extended Data Out (EDO) Performance:
-50 tRAC tCAC tAA tRC tHPC RAS Access Time CAS Access Time Access Time from Address Cycle Time EDO Mode Cycle Time 50 ns 13 ns 25 ns 84 ns 20 ns -60 60 ns 15 ns 30 ns 104 ns 25 ns
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* * * * * *
Single +3.3 V 0.3 V Power Supply CAS-before-RAS refresh, RAS-only-refresh Decoupling capacitors mounted on substrate All inputs, outputs and clocks are fully LV-TTL compatible Serial presence detects (optional) Utilizes four 1M x 16 -DRAMs in TSOPII-50/44 and two 1M x 4 - DRAMs in SOJ 26/20 packages 1024 refresh cycles / 16 ms with 10 / 10 addressing (Row / Column) Gold contact pad Card Size: 133,35mm x 25,40 mm x 5,30 mm This DRAM product module family is intended to be fully pin and architecture compatible with the 168pin unbuffered SDRAM DIMM module family
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Semiconductor Group
1
2.97
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
The HYM64(72)V1005GU-50/-60 are industry standard 168-pin 8-byte Dual In-Line Memory Module (DIMMs) which are organized as 1M x 64 and 1M x 72 high speed memory arrays designed with EDO DRAMs for non-parity and ECC applications. The DIMMs use four 1M x 16 EDO DRAMs for the 1M x 64 organisation and additional two 1M x 4 DRAMs for the 1M x 72 organisation. Decoupling capacitors are mounted on the PC board. The DIMMs use optional serial presence detects implemented via a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes of serial PD data are available to the customer. All 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long spacesaving footprint.
Ordering Information Type
HYM 64V1005GU-50 HYM 64V1005GU-60 HYM 72V1005GU-50 HYM 72V1005GU-60
Ordering Code
Q67100-Q2176 Q67100-Q2177 Q67100-Q2178 Q67100-Q2179
Package
L-DIM-168-10 L-DIM-168-10 L-DIM-168-10 L-DIM-168-10
Descriptions
1M x 64 DRAM module (access time 50 ns) 1M x 64 DRAM module (access time 60 ns) 1M x 72 DRAM module (access time 50 ns) 1M x 72 DRAM module (access time 60 ns)
Pin Names A0-A9 DQ0 - DQ63 CB0-CB7 RAS0, RAS2 CAS0 - CAS7 WE0, WE2 OE0, OE2 Vcc Vss SCL SDA SA0-SA2 N.C. DU Address Input Data Input/Output Check Bit Data Input/Output ( x72 only) Row Address Strobe Column Address Strobe Read / Write Input Output Enable Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect Serial Presence Detect Addresses No Connection Don' use t
Semiconductor Group
2
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
Pin Configuration
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE0 CAS0 CAS1 RAS0 OE0 VSS A0 A2 A4 A6 A8 NC NC VCC VCC DU PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol VSS OE2 RAS2 CAS2 CAS3 WE2 VCC NC NC CB3 CB3 VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VCC PIN # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC DU CAS4 CAS5 NC DU VSS A1 A3 A5 A7 A9 NC NC VCC DU DU PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS DU NC CAS6 CAS7 DU VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS NC NC SA0 SA1 SA2 VCC
Semiconductor Group
3
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
RAS0 WE0 OE0 OE CAS0 DQ0-DQ7 WE RAS
RAS2 WE2 OE2 OE CAS4 DQ32-DQ39 WE RAS
LCAS I/O1-I/O8
LCAS I/O1-I/O8
CAS1 DQ8-DQ15
UCAS I/O9-I/O16
CAS5 DQ40-DQ47
UCAS I/O9-I/O16
D1
OE CAS2 DQ16-DQ23 WE RAS CAS6 DQ48-DQ55 OE WE
D3
RAS
LCAS I/O1-I/O8
LCAS I/O1-I/O8
CAS3 DQ24-DQ31
UCAS I/O9-I/O16
CAS7 DQ56-DQ63
UCAS I/O9-I/O16
D2
D4
A0-A9 VCC
D1,D2,D3,D4
E2PROM (256wordx8bit)
C1-C4 VSS
SA0 SA1 SA2
SCL SDA
1M x 64 DIMM Module Block Diagram
Semiconductor Group
4
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
RAS0 WE0 OE0 OE CAS0 DQ0-DQ7 WE RAS
RAS2 WE2 OE2 OE CAS4 DQ32-DQ39 WE RAS
LCAS I/O1-I/O8
LCAS I/O1-I/O8
CAS1 DQ8-DQ15
UCAS I/O9-I/O16
CAS5 DQ40-DQ47
UCAS I/O9-I/O16
D0
OE CAS CB0-CB3 I/O1-I/O4 D4 OE CAS2 DQ16-DQ23 WE RAS CAS6 DQ48-DQ55 OE WE CB4-CB7 WE RAS OE CAS I/O1-I/O4 WE
D2
RAS
D5 RAS
LCAS I/O1-I/O8
LCAS I/O1-I/O8
CAS3 DQ24-DQ31
UCAS I/O9-I/O16
CAS7 DQ56-DQ63
UCAS I/O9-I/O16
D1
D3
A0-A9 VCC
D0-D5
E2PROM (256wordx8bit)
C0-C5 VSS
SA0 SA1 SA2
SCL SDA
1M x 72 DIMM Module Block Diagram
Semiconductor Group
5
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
TRUTH TABLE
FUNCTION Standby Read Early-Write Late-Write Read-Modify-Write (RMW) EDO Page Mode Read 1st Cycle 2nd Cycle EDO Page Mode Write 1st Cycle 2nd Cycle EDO Page Mode RMW 1st Cycle 2st Cycle RAS only refresh CAS-before-RAS refresh Hidden Refresh READ WRITE Self Refresh
RAS H L L L L L L L L L L L H-L L-H-L L-H-L H-L
CAS X L L L L H-L H-L H-L H-L H-L H-L H L L L L
WRITE X H L H-L H-L H H L L H-L H-L X H H L H
OE X L X H L-H L L X X L-H L-H X X L X X
ROW ADDR X ROW ROW ROW ROW ROW n/a ROW n/a ROW n/a ROW X ROW ROW X
COL ADDR X COL COL COL COL COL COL COL COL COL COL n/a n/a COL COL X
DQ0-DQ63 High Impedance Data Out Data In Data In Data Out, Data In Data Out Data Out Data In Data In Data Out, Data In Data Out, Data In High Impedance High Impedance Data Out Data In High Impedance
Semiconductor Group
6
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Input/output voltage .............................................................................. -0.5 to min (Vcc+0.5, 4.6) V Power supply voltage.................................................................................................... -0.5 to 4.6 V Power dissipation.................................................................................................................. 4.42 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C; VCC = 3.3 V 0.3 V Parameter Input high voltage Input low voltage Output high voltage (LVTTL) Output "level voltage ( IOUT = - 2 mA) H Output low voltage (LVTTL) Output " level voltage ( IOUT = + 2 mA) L Output high voltage (LVCMOS) Output "level voltage ( IOUT =- 100A) H Output low voltage (LVCMOS) Output " level voltage ( IOUT =+100 A) L Input leakage current (0 V < VIN < Vcc, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < Vcc) Symbol min. x 64/ x72 max. Vcc + 0.5 V 0.8 - 0.4 - 0.4 10 +10 V V V V V A A 1) 1) 1) 1) 1) 1) 1) 1) 2.0 - 0.5 2.4 - Vcc-0.2 - - 10 - 10 Unit Notes
VIH VIL VOH VOL VOH VOL II(L) IO(L)
Semiconductor Group
7
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
DC Characteristics (cont' ) d TA = 0 to 70 C; VCC = 3.3 V 0.3 V Parameter Average VCC supply current: -50 version -60 version (RAS,CAS,address cycling, tRC=tRC min.) Standby VCC supply current ICC2 (RAS = CAS = VIH, one address change) Average VCC supply current during RAS ICC3 only refresh cycles: -50 version -60 version (RAS cycling, CAS = VIH , t RC = tRC min.) Average VCC supply current during ICC4 hyper page mode (EDO): -50 version -60 version (RAS = VIL, CAS, address cycling tPC = tPC min.) Standby VCC supply current (RAS = CAS = VCC - 0.2 V, one address change) - 16 - 18 mA - Symbol min. x 64 max. 800 720 min. - - x 72 max. 940 840 Unit Note s mA mA
2) 3) 4)
ICC1
- -
2) 4)
- -
800 720
- -
940 840
mA mA
- -
360 300
- -
500 420
mA mA
2) 3) 4)
ICC5
-
8
-
9
mA
-
ICC6 Average VCC supply current during CAS-before-RAS refresh mode: -50 version -60 version
(RAS, CAS cycling, tRC = tRC min.)
- -
800 720
- -
940 840
mA mA
2) 4)
Semiconductor Group
8
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. max. - - 10k 10k - - - - 37 25 min. 104 40 60 10 0 10 0 10 14 12 15 50 - 50 16 5 1 - -60 max. - - 10k 10k - - - - 45 30 - - - 50 16
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 84 30 50 8 0 8 0 8 12 10 13 40 5 1 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time tRAC tCAC tAA tOEA tRAL tRCS tRCH - - - - 25 0 0 0 0 0 0 50 13 25 13 - - - - - 13 13 - - - - 30 0 0 0 0 0 0 60 15 30 15 - - - - - 15 15 ns ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 8, 9 8, 9 8,10
Read command hold time referenced to tRRH RAS CAS to output in low-Z Output buffer turn-off delay Output turn-off delay from OE tCLZ tOFF tOEZ
Semiconductor Group
9
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
AC Characteristics (cont' 5)6) d) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. max. - - - - min. 0 0 13 13 -60 max. - - - -
Unit
Note
Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tDZC tDZO tCDD tODD
0 0 10 10
ns ns ns ns
13 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 8 - - - - - - - 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time tRWC tRWD tCWD tAWD tOEH 113 64 27 39 10 - - - - - 138 77 32 47 13 - - - - - ns ns ns ns ns 15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS Delay OE setup time prior to CAS tHPC tCP tCPA tCOH tRAS tRHPC tOES 20 8 - 5 50 27 5 - - 27 - 200k - - 25 10 - 5 60 32 5 - - 32 - 200k - - ns ns ns ns ns ns ns 7
Semiconductor Group
10
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
AC Characteristics (cont' 5)6) d) TA = 0 to 70 C,VCC = 3.3 V 0.3 V, tT = 2 ns Parameter
Symbol
16E
Limit Values -50 min. max. - - min. 68 49 -60 max. - -
Unit
Note
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write cycle time CAS precharge to WE tPRWC tCPWD 58 41 ns ns
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Capacitance TA = 0 to 70 C; VCC = 3.3 V 0.3 V; f = 1 MHz Parameter Input Capacitance (A0 to A9) Input Capacitance (RAS0, RAS2) Input Capacitance (CAS0-CAS7) Input Capacitance (WE0,WE2,OE0,OE2) I/O Capacitance (DQ0-DQ63,CB0-CB8) Input Capacitance (SCL, SA0-2) Input/Output Capacitance (SDA) Symbol min. Limit Values max. 55 50 10 50 11 8 10 pF pF pF pF pF pF pF - - - - - - - Unit
CI1 CI2 CI3 CI4 CIO1
Cs Cs
Semiconductor Group
11
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume
tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of t RAC, tCAC, tAA,tCPA ,tOEA. t CAC is measured from tristate. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS , tRWD , tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.) , tCWD > tCWD (min.) and tAWD > tAWD (min.) , the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.
Semiconductor Group
12
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
Serial Presence Detects: A serial presence detect storage device -- EEPROM 24C02 -- is assembled on to the module. Information about the modul confuguration, speed, etc. is written into the EEPROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus).
64 V1005 GU-50 0 Number of SPD bytes 128 80 1 Total bytes in Serial PD 256 08 2 Memory Type EDO 02 3 Number of Row Addresses 10 0A 4 Number of Column Addresses 10 0A 5 Number of DIMM Banks 1 01 6 Module Data Width x64 / x72 40 7 Module Data Width (cont' d) 0 00 8 Module Interface Levels LVTTL 01 9 RAS access time 50 / 60 ns 32 10 CAS access time 13 / 15 ns 0D 11 Dimm Config (Error Det/Corr.) none / ECC 00 12 Refresh Rate/Type normal 00 15.6s 13 Primary DRAM data width x16 10 14 Error checking DRAM data width none / x4 00 15-31 reserved for future offerings FF 32 Superset Memory Type NA FF 33-61 Superset information (may be used in NA FF future) 62 SPD Revision Designator Rev. 1.0 01 63 Checksum for bytes 0-62 XX 64-127 Manufacturer Information (optional) FF 128- Unused Storage Locations FF 255
Byte# Description SPD Entry Value
Hex HYM 64 V1005 GU-60 80 08 02 0A 0A 01 40 00 01 3C 0F 00 00 10 00 FF FF FF 01 XX FF FF 72 V1005 GU-50 80 08 02 0A 0A 01 48 00 01 32 0D 02 00 10 04 FF FF FF 01 XX FF FF 72 V1005 GU-60 80 08 02 0A 0A 01 48 00 01 3C 0F 02 00 10 04 FF FF FF 01 XX FF FF
Semiconductor Group
13
HYM 64(72)V1005GU-50/-60 1M x 64/72 DRAM Module
L-DIM-168-10 Module package (168 pin, dual read-out, single in-line memory module)
133,35 127,35 5,6
3,0
1
10 11 42,18 66,68
A B
40
41
84
C
85
94 95
124
125
168
6,35 3,125 3,125
6,35 1,27 2,54 min. 1,0 + 0.5 -
2,0 Detail A Detail B
2,0
Detail C
DM168-10.WMF
preliminary drawing
Semiconductor Group
14
17,78
0,2+ 0,15 -
25,40

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